1. Field of the Invention
This invention relates to nonvolatile MNOS transistor memory arrays employing single-element-per-bit storage and two-element-per-bit sensing.
2. Description of the Prior Art
As their development has progressed over the last several years, MNOS devices have seen increased use in the design and fabrication of memory arrays. The MNOS device is particularly desirable because of its nonvolatility; that is, the information written into the device is retained even in a power-off state. An MNOS device normally will take the form of a standard insulated gate field effect transistor structure in which the silicon dioxide gate insulator is replaced by a double insulator, typically a layer of silicon dioxide nearest the silicon substrate and a layer of silicon nitride over the silicon dioxide. The "memory" of the device is associated with the existence of traps at or near the silicon dioxide-silicon nitride interface, the threshold voltage of the insulator-gate field effect transistor being influenced by the charged state of the traps. These traps are conveniently charged and discharged by the application of a sufficiently large voltage of suitable effective polarity to the gate electrode. The MNOS memory device can then be assigned a high or low logic level dependent upon the written threshold voltage level.
Although the MNOS device can be correctly deemed as nonvolatile, repeated interrogation of the device can, after a large number of such interrogations, cause deterioration of the performance of the device, necessitating a "refresh" pulse to the gate of the device. The information content of the MNOS device is accessed by a sense circuit which includes the interrogation step mentioned above. The design of the sense circuit directly affects the storage density of the larger MNOS memory array. Although a single-element-per-bit storage configuration is highly desirable, two-element-per-bit storage configurations are prevalent. Apparently the absence of a commercially available single-element-per-bit storage memory array is due to the lack of a suitable sense amplifier circuit, thereby forcing the use of the bulkier two-element-per-bit configurations.